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? freescale semiconductor, inc., 2003?2007. all rights reserved. freescale semiconductor technical data this hardware specification cont ains detailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for the mpc875/mpc870. the cpu on the mpc875/mpc870 is a 32-bit core built on power architecture? technology that incorporates memory management units (mmus) and instruction and data caches. for functional characteristics of the mpc875/mpc870, refer to the mpc885 powerquicc? family reference manual. to locate published errata or updates for this document, refer to the mpc875/mpc870 product summary page on our website listed on the back cover of this document or, contact your local freescale sales office. document number: mpc875ec rev. 4, 08/2007 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3. maximum tolerated ratings . . . . . . . . . . . . . . . . . . . 9 4. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . 10 5. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. thermal calculation and measurement . . . . . . . . . . 12 8. power supply and power sequencing . . . . . . . . . . . 14 9. mandatory reset configurations . . . . . . . . . . . . . . . 15 10. layout practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11. bus signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12. ieee 1149.1 electrical specifications . . . . . . . . . . . 45 13. cpm electrical characteristics . . . . . . . . . . . . . . . . . 47 14. usb electrical characteristics . . . . . . . . . . . . . . . . . 67 15. fec electrical characteristics . . . . . . . . . . . . . . . . . 67 16. mechanical data and ordering information . . . . . . . 71 17. document revision history . . . . . . . . . . . . . . . . . . . 80 mpc875/mpc870 powerquicc? hardware specifications
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 2 freescale semiconductor overview 1overview the mpc875/mpc870 is a versatile single-chip inte grated microprocessor and peripheral combination that can be used in a variety of controller appli cations and communications and networking systems. the mpc875/mpc870 provides enhanced atm functionality ove r that of other atm-enabled members of the mpc860 family. table 1 shows the functionality supported by the mpc875/mpc870. 2features the mpc875/mpc870 is comprised of three modules that each use the 32-bit internal bus: a mpc8xx core, a system integration unit (siu), and a communications processor module (cpm). the following list summarizes the key mpc875/mpc870 features: ? embedded mpc8xx core up to 133 mhz ? maximum frequency operation of the ex ternal bus is 80 mhz (in 1:1 mode) ? the 133-mhz core frequency supports 2:1 mode only ? the 66-/80-mhz core frequencies support both the 1:1 and 2:1 modes ? single-issue, 32-bit core (compatible with the power architecture definition) with thirty-two 32-bit general-purpose registers (gprs) ? the core performs branch prediction with conditional prefetch and without conditional execution ? 8-kbyte data cache and 8-kbyte instruction cache (see table 1 ) ? instruction cache is two-way, set-associative with 256 sets in 2 blocks ? data cache is two-way, set-associative with 256 sets ? cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks ? caches are physically addressed, implement a least recently used (lru) replacement algorithm, and are lockable on a cache block basis ? mmus with 32-entry tlb, fully associative instruction and data tlbs ? mmus support multiple page sizes of 4, 16, a nd 512 kbytes, and 8 mbytes; 16 virtual address spaces and 16 protection groups ? advanced on-chip emulation debug mode ? up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) table 1. mpc875/mpc870 devices part cache (kbytes) ethernet scc smc usb security engine i cache d cache 10baset 10/100 m p c 8 7 5 8812111y e s mpc870 8 8 ? 2 ? 1 1 no
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 3 features ? thirty-two address lines ? memory controller (eight banks) ? contains complete dynamic ram (dram) controller ? each bank can be a chip select or ras to support a dram bank ? up to 30 wait states programmable per memory bank ? glueless interface to dram, simms, sram, eproms, flash eproms, and other memory devices ? dram controller programmable to support most size and speed memory interfaces ? four cas lines, four we lines, and one oe line ? boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) ? variable block sizes (32 kbytes?256 mbytes) ? selectable write protection ? on-chip bus arbitration logic ? general-purpose timers ? four 16-bit timers or two 32-bit timers ? gate mode can enable/disable counting ? interrupt can be masked on reference match and event capture ? two fast ethernet controllers (fec)?two 10/100 mbps ethernet/ieee std. 802.3? cdma/cs that interface through mii and/or rmii interfaces ? system integration unit (siu) ? bus monitor ? software watchdog ? periodic interrupt timer (pit) ? clock synthesizer ? decrementer and time base ? reset controller ? ieee 1149.1? std. test access port (jtag) ? security engine is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, ieee 802.11i? standard, and iscsi processing. available on the mpc875, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (chas). the chas are: ? data encryption standard execution unit (deu) ? des, 3des ? two key (k1, k2, k1) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rijndael symmetric key cipher
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 4 freescale semiconductor features ? ecb, cbc, and counter modes ? 128-, 192-, and 256-bit key lengths ? message digest execution unit (mdeu) ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? master/slave logic, with dma ? 32-bit address/32-bit data ? operation at mpc8xx bus frequency ? crypto-channel supporting multi-command descriptors ? integrated controller managing crypto-execution units ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? interrupts ? six external interrupt request (irq) lines ? twelve port pins with interrupt capability ? twenty-three internal interrupt sources ? programmable priority between sccs ? programmable highest priority request ? communications processor module (cpm) ? risc controller ? communication-specific commands (for example, graceful stop transmit , enter hunt mode , and restart transmit ) ? supports continuous mode transmission and reception on all serial channels ? 8-kbytes of dual-port ram ? several serial dma (sdma) channels to support the cpm ? three parallel i/o registers with open-drain capability ? on-chip 16 16 multiply accumulate controller (mac) ? one operation per clock (two-clo ck latency, one-clock blockage) ? mac operates concurrently with other instructions ? fir loop?four clocks per four multiplies ? four baud-rate generators ? independent (can be connected to scc or smc) ? allows changes during operation ? autobaud support option ? scc (serial communication controller) ? ethernet/ieee 802.3? standard, supporting full 10-mbps operation ? hdlc/sdlc
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 5 features ? hdlc bus (implements an hdlc-based local area network (lan)) ? asynchronous hdlc to support point-to-point protocol (ppp) ? appletalk ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? serial infrared (irda) ? binary synchronous communication (bisync) ? totally transparent (bit streams) ? totally transparent (frame based with optional cyclic redundancy check (crc)) ? smc (serial management channel) ? uart (low-speed operation) ? transparent ? universal serial bus (usb)?supports opera tion as a usb function endpoint, a usb host controller, or both for testing purposes (loopback diagnostics) ? usb 2.0 full-/low-speed compatible ? the usb function mode has the following features: ? four independent endpoints support control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? crc5 checking ? nrzi encoding/decoding with bit stuffing ? 12- or 1.5-mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error ? the usb host controller has the following features: ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decoding with bit stuffing ? supports both 12- and 1.5-mbps data rates (a utomatic generation of preamble token and data rate configuration). note that low-speed operation requires an external hub. ? flexible data buffers with multiple buffers per frame ? supports local loopback mode for diagnostics (12 mbps only) ? serial peripheral interface (spi) ? supports master and slave modes ? supports multiple-master operation on the same bus ? inter-integrated circuit (i 2 c) port ? supports master and slave modes ? supports a multiple-master environment
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 6 freescale semiconductor features ? the mpc875 has a time-slot assigner (tsa) that supports one tdm bus (tdmb) ? allows scc and smc to run in multip lexed and/or non-multiplexed operation ? supports t1, cept, pcm highway, isdn basic rate, isdn primary rate, user-defined ? 1- or 8-bit resolution ? allows independent transmit and receive r outing, frame synchronization, and clocking ? allows dynamic changes ? can be internally connected to two serial channels (one scc and one smc) ? pcmcia interface ? master (socket) interface, release 2.1-compliant ? supports one independent pcmcia socket on the mpc875/mpc870 ? eight memory or i/o windows supported ? debug interface ? eight comparators: four operate on instruction address, two operate on data address, and two operate on data ? supports conditions: = <> ? each watchpoint can generate a break point internally ? normal high and normal low power modes to conserve power ? 1.8-v core and 3.3-v i/o operation with 5-v ttl compatibility ? the mpc875/mpc870 comes in a 256-pin ball grid array (pbga) package
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 7 features the mpc875 block diagram is shown in figure 1 . figure 1. mpc875 block diagram bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram system functions 8-kbyte instruction cache 32-entry itlb instruction mmu 8-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom serial interface spi smc1 mpc8xx processor core scc4 pcmcia-ata interface virtual idma and serial dmas security engine aesu deu mdeu controller channel dmas dmas fifos 10/100 miii/rmii baset media access control fast ethernet controller usb slave/master if dmas i 2 c time-slot assigner port bus interface
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 8 freescale semiconductor features the mpc870 block diagram is shown in figure 2 . figure 2. mpc870 block diagram bus system interface unit (siu) embedded parallel i/o memory controller 4 timers interrupt controllers 8-kbyte dual-port ram system functions 8-kbyte instruction cache 32-entry itlb instruction mmu 8-kbyte data cache 32-entry dtlb data mmu instruction bus load/store bus unified 4 baud rate generators parallel interface internal bus interface unit external bus interface unit timers 32-bit risc controller and program rom serial interface spi smc1 mpc8xx processor core pcmcia-ata interface virtual idma and serial dmas dmas dmas fifos 10/100 miii/rmii baset media access control fast ethernet controller usb slave/master if dmas i 2 c port bus interface
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 9 maximum tolerated ratings 3 maximum tolerated ratings this section provides the maximum tolerated volta ge and temperature ranges for the mpc875/mpc870. table 2 displays the maximum tolerated ratings and table 3 displays the operating temperatures. figure 3 shows the undershoot and overshoot voltages at the interfaces of the mpc875/mpc870. figure 3. undershoot/overshoot voltage for v ddh and v ddl table 2. maximum tolerated ratings rating symbol value unit supply voltage 1 1 the power supply of the device must start its ramp from 0.0 v. v ddl (core voltage) ?0.3 to 3.4 v v ddh (i/o voltage) ?0.3 to 4 v v ddsyn ?0.3 to 3.4 v difference between v ddl and v ddsyn <100 mv input voltage 2 2 functional operating conditions are provided with the dc electrical specifications in ta ble 6 . absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. caution : all inputs that tolerate 5 v cannot be more than 2.5 v greater than v ddh . this restriction applies to power up and normal operation (that is, if the mpc875/mpc870 is unpowered, a voltage greater than 2.5 v must not be applied to its inputs). v in gnd ? 0.3 to v ddh v storage temperature range t stg ?55 to +150 c gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% v ddh /v ddl + 20% v ddh /v ddl v ddh /v ddl + 5% of t interface 1 1. t interface refers to the clock period associated with the bus clock interface. v ih v il note:
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 10 freescale semiconductor thermal characteristics this device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be take n to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circ uit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic vo ltage level (for example, either gnd or v ddh ). 4 thermal characteristics table 4 shows the thermal characteristics for the mpc875/mpc870. table 3. operating temperatures rating symbol value unit temperature 1 (standard) 1 minimum temperatures are guaranteed as ambient temperature, t a . maximum temperatures are guaranteed as junction temperature, t j . t a(min) 0c t j(max) 95 c temperature (extended) t a(min) ?40 c t j(max) 100 c table 4. mpc875/mpc870 thermal resistance data rating environment symbol value unit junction-to-ambient 1 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. natural convection single-layer board (1s) r ja 2 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 43 c/w four-layer board (2s2p) r jma 3 3 per jedec jesd51-6 with the board horizontal. 29 airflow (200 ft/min) single-layer board (1s) r jma 3 36 four-layer board (2s2p) r jma 3 26 junction-to-board 4 4 thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 20 junction-to-case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance. r jc 10 junction-to-package top 6 6 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. natural convection jt 2 airflow (200 ft/min) jt 2
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 11 power dissipation 5 power dissipation table 5 provides information on power dissipation. the modes are 1:1, where cpu and bus speeds are equal, and 2:1, where cpu frequency is twice bus speed. note the values in table 5 represent v ddl -based power dissipation and do not include i/o power dissipation over v ddh . i/o power dissipation varies widely by application due to buffer current, depending on external circuitry. the v ddsyn power dissipation is negligible. 6 dc characteristics table 6 provides the dc electrical ch aracteristics for the mpc875/mpc870. table 5. power dissipation (p d ) die revision bus mode frequency typical 1 1 typical power dissipation is measured at v ddl = v ddsyn = 1.8 v, and v ddh is at 3.3 v. maximum 2 2 maximum power dissipation at v ddl = v ddsyn = 1.9 v, and v ddh is at 3.5 v. unit 0 1:1 66 mhz 310 390 mw 80 mhz 350 430 mw 2:1 133 mhz 430 495 mw table 6. dc electrical specifications characteristic symbol min max unit operating voltage v ddh (i/o) 3.135 3.465 v v ddl (core) 1.7 1.9 v v ddsyn 1 1.7 1.9 v difference between v ddl and v ddsyn ?1 0 0m v input high voltage (all inputs except extal and extclk) 2 v ih 2.0 3.465 v input low voltage 3 v il gnd 0.8 v extal, extclk input high voltage v ihc 0.7 v ddh v ddh v input leakage current, v in = 5.5 v (except tms, trst , dsck, and dsdi pins) for 5-v tolerant pins 1 i in ? 100 a input leakage current, v in = v ddh (except tms, trst , dsck, and dsdi) i in ?1 0 a input leakage current, v in = 0 v (except tms, trst , dsck, and dsdi pins) i in ?1 0 a input capacitance 4 c in ?2 0p f
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 12 freescale semiconductor thermal calculation and measurement 7 thermal calculation and measurement for the following discussions, p d = (v ddl i ddl ) + p i/o , where p i/o is the power dissipation of the i/o drivers. note the v ddsyn power dissipation is negligible. 7.1 estimation with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , in c can be obtained from the following equation: t j = t a + (r ja p d ) where: t a = ambient temperature ( c) r ja = package junction-to-ambient thermal resistance ( c/w) p d = power dissipation in package the junction-to-ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. however, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity t j ? t a ) are possible. output high voltage, i oh = ?2.0 ma, v ddh = 3.0 v (except xtal and open-drain pins) v oh 2.4 ? v output low voltage i ol = 2.0 ma (clkout) i ol = 3.2 ma 5 i ol = 5.3 ma 6 i ol = 7.0 ma (txd1/pa14, txd2/pa12) i ol = 8.9 ma (ts , ta , tea , bi , bb , hreset , sreset ) v ol ?0 . 5v 1 the difference between v ddl and v ddsyn cannot be more than 100 mv. 2 the signals pa[0:15], pb[14:31], pc[4:15], pd[3:15], pe(14:31), tdi, tdo, tck, trst , tms, mii1_txen, and mii_mdio are 5-v tolerant. the minimum voltage is still 2.0 v. 3 v il (max) for the i 2 c interface is 0.8 v rather than the 1.5 v as specified in the i 2 c standard. 4 input capacitance is periodically sampled. 5 a(0:31), tsiz0/reg , tsiz1, d(0:31), irq (2:4), irq6 , rd/wr , burst , ip_b(0:1), pa(0:4), pa(6:7), pa(10:11), pa15, pb19, pb(23:31), pc(6:7), pc(10:13), pc15, pd8, pe(14:31), mii1_crs, mii_mdio, mii1_txen, and mii1_col. 6 bdip /gpl_b (5), br , bg , frz/irq6 , cs (0:7), we (0:3), bs _a(0:3), gpl_a0 /gpl_b0 , oe /gpl_a1 /gpl_b1 , gpl_a (2:3)/gpl_b (2:3)/cs (2:3), upwaita/gpl_a4 , upwaitb/gpl_b4 , gpl_a5 , ale_a, ce 1 _a, ce 2 _a, op(0:3), and baddr(28:30). table 6. dc electrical specifications (continued) characteristic symbol min max unit
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 13 thermal calculation and measurement 7.2 estimation with junction-to-case thermal resistance historically, thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( c/w) r jc = junction-to-case thermal resistance ( c/w) r ca = case-to-ambient thermal resistance ( c/w) r jc is device-related and cannot be influenced by the user. the user adjusts the thermal environment to affect the case-to-ambient thermal resistance, r ca . for instance, the user can change the airflow around the device, add a heat sink, change the mounting arra ngement on the printed-circ uit board, or change the thermal dissipation on the printed-circuit board surrounding the device. this thermal model is most useful for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink to the ambient environment. for most packages, a better model is required. 7.3 estimation with junction-to-board thermal resistance a simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a juncti on-to-case thermal resistance. the junction-to-case thermal resistance covers the situation where a heat si nk is used or where a substantial amount of heat is dissipated from the top of the package. the juncti on-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j = t b + (r jb p d ) where: r jb = junction-to-board thermal resistance ( c/w) t b = board temperature ( c) p d = power dissipation in package if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.4 estimation using simulation when the board temperature is not known, a thermal s imulation of the application is needed. the simple two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation.
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 14 freescale semiconductor power supply and power sequencing 7.5 experimental determination to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top cente r of the package case using the following equation: t j = t t + ( jt p d ) where: jt = thermal characterization parameter t t = thermocouple temperature on top of package p d = power dissipation in package the thermal characterization parameter is measur ed per the jesd51-2 specification published by jedec using a 40 gauge type t thermocouple epoxied to the top center of the packag e case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. 7.6 references semiconductor equipment and materi als international (415) 964-5111 805 east middlefield rd mountain view, ca 94043 mil-spec and eia/jesd (jedec) specifications 800-854-7179 or (available from global engineering documents) 303-397-7956 jedec specifications http://www.jedec.org 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? procee dings of semitherm, san diego, 1998, pp. 47?54. 2. 2. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of semitherm, san diego, 1999, pp. 212?220. 8 power supply and power sequencing this section provides design considerations for the mpc875/mpc870 power supply. the mpc875/mpc870 has a core voltage (v ddl ) and pll voltage (v ddsyn ), which both operate at a lower voltage than the i/o voltage (v ddh ). the i/o section of the mpc875/mpc870 is supplied with 3.3 v across v ddh and v ss (gnd). the signals pa[0:3], pa[8:11], pb15, pb[24:25], pb[28:31], pc[4:7], pc[12:13], pc15, pd[3:15], tdi, tdo, tck, trst , tms, mii_txen, and mii_mdio are 5 v tolerant. no input can be more than 2.5 v greater than v ddh . in addition, 5-v tolerant pins cannot exceed 5.5 v, and remaining input pins cannot exceed 3.465 v. this restriction applies to power up, power down, and normal operation.
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 15 mandatory reset configurations one consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp up at different rates. the rates depend on the nature of the power supply, the type of load on each power supply, and the manner in which different voltage s are derived. the following restrictions apply: ?v ddl must not exceed v ddh during power up and power down ?v ddl must not exceed 1.9 v, and v ddh must not exceed 3.465 v these cautions are necessary for the long-term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes are forward-bias ed, and excessive current can flow through these diodes. if the system power supply design does not cont rol the voltage sequencing, the circuit shown in figure 4 can be added to meet these requirements. the mur420 schottky diodes control the maximum potential difference between the external bus and core power supplies on power up, and the 1n5820 diodes regulate the maximum potential difference on power down. figure 4. example voltage sequencing circuit 9 mandatory reset configurations the mpc875/mpc870 requires a mandatory configuration during reset. if hardware reset configuration word (hrcw) is enabled, the hrcw[dbgc] value needs to be set to binary x1 in the hrcw and the siumcr[dbgc] should be programmed with the same value in the boot code after reset. this can be done by asserting the rstconf during hreset assertion. if hrcw is disabled, the siumcr[dbgc] should be programmed with binary x1 in the boot code after reset by negating the rstconf during the hreset assertion. the mbmr[gplb4dis], papar, padir, pbpar, pbdir, pcpar, and pcdir need to be configured with the mandatory values in table 7 in the boot code after the reset is negated. table 7. mandatory reset configuration of mpc875/mpc870 register/configuration field value (binary) hrcw (hardware reset configuration word) hrcw[dbgc] x1 siumcr (siu module configuration register) siumcr[dbgc] x1 mbmr (machine b mode register) mbmr[gplb4dis} 0 papar (port a pin assignment register) papar[5:9] pa pa r [ 1 2: 1 3] 0 v ddh v ddl 1n5820 mur420
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 16 freescale semiconductor layout practices 10 layout practices each v dd pin on the mpc875/mpc870 should be provided with a low-impedance path to the board?s supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v dd power supply should be bypassed to ground using at least four 0.1-f bypass capacitors located as close as possible to the four sides of the package. each board designed should be characterized and a dditional appropriate decoupl ing capacitors should be used if required. the capacitor leads and associated printed-circuit traces connecting to chip v dd and gnd should be kept to less than half an inch pe r capacitor lead. at a minimum, a four-layer board employing two inner layers as v dd and gnd planes should be used. all output pins on the mpc875/mpc870 have fast ri se and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation pa rticularly applies to th e address and data buses. maximum pc trace lengths of 6 inches are recommende d. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems w ith higher capacitive loads because these loads create higher transient currents in the v dd and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. for more information, refer to section 14.4.3, ?clock synthesizer power (v ddsyn , v sssyn , v sssyn1 ),? in the mpc885 powerquicc? family reference manual . padir (port a data direction register) padir[5:9] padir[12:13] 0 pbpar (port b pin assignment register) pbpar[14:18] pbpar[20:22] 0 pbdir (port b data direction register) pbdir[14:8] pbdir[20:22] 0 pcpar (port c pin assignment register) pcpar[4:5] pcpar[8:9] pcpar[14] 0 pcdir (port c data direction register) pcdir[4:5] pcdir[8:9] pcdir[14] 0 pdpar (port d pin assignment register) pdpar[3:7] pdpar[9:5] 0 pddir (port d data direction register) pddir[3:7] pddir[9:15] 0 table 7. mandatory reset configuration of mpc875/mpc870 (continued) register/configuration field value (binary)
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 17 bus signal timing 11 bus signal timing the maximum bus speed supported by the mpc875/mpc870 is 80 mhz. higher-speed parts must be operated in half-speed bus mode (for example, an mpc875/mpc870 used at 133 mhz must be configured for a 66 mhz bus). table 8 shows the frequency ranges for standard part frequencies in 1:1 bus mode, and table 9 shows the frequency ranges for standard part frequencies in 2:1 bus mode. table 10 provides the bus operation timing for the mpc875/mpc870 at 33, 40, 66, and 80 mhz. the timing for the mpc875/mpc870 bus shown table 10 , assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. clkout assumes a 100-pf load maximum delay table 8. frequency ranges for standard part frequencies (1:1 bus mode) part frequency 66 mhz 80 mhz min max min max core frequency 40 66.67 40 80 bus frequency 40 66.67 40 80 table 9. frequency ranges for standard part frequencies (2:1 bus mode) part frequency 66 mhz 80 mhz 133 mhz min max min max min max core frequency 40 66.67 40 80 40 133 bus frequency 20 33.33 20 40 20 66 table 10. bus operation timings num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max b1 bus period (clkout), see ta b l e 8 ????????ns b1a extclk to clkout phase skew?if clkout is an integer multiple of extclk, then the rising edge of extclk is aligned with the rising edge of clkout. for a non-integer multiple of extclk, this synchronization is lost, and the rising edges of extclk and clkout have a continuously varying phase skew. ?2 +2 ?2 +2 ?2 +2 ?2 +2 ns b1b clkout frequency jitter peak-to-peak ? 1 ? 1 ? 1 ? 1 ns b1c frequency jitter on extclk ? 0.50 ? 0.50 ? 0.50 ? 0.50 % b1d clkout phase jitter peak-to-peak for osclk 15 mhz ?4?4?4?4ns clkout phase jitter peak-to-peak for osclk < 15 mhz ?5?5?5?5ns
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 18 freescale semiconductor bus signal timing b2 clkout pulse width low (min = 0.4 b1, max = 0.6 b1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns b3 clkout pulse width high (min = 0.4 b1, max = 0.6 b1) 12.1 18.2 10.0 15.0 6.1 9.1 5.0 7.5 ns b4 clkout rise time ? 4.00 ? 4.00 ? 4.00 ? 4.00 ns b5 clkout fall time ? 4.00 ? 4.00 ? 4.00 ? 4.00 ns b7 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31) output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b7a clkout to tsiz(0:1), reg , rsv , bdip , ptr output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2) iwp(0:2), lwp(0:1), sts output hold (min = 0.25 b1) 7.60 ? 6.30 ? 3.80 ? 3.13 ? ns b8 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31) valid (max = 0.25 b1 + 6.3) ? 13.80 ? 12.50 ? 10.00 ? 9.43 ns b8a clkout to tsiz(0:1), reg , rsv , bdip , ptr valid (max = 0.25 b1 + 6.3) ? 13.80 ? 12.50 ? 10.00 ? 9.43 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 2 (max = 0.25 b1 + 6.3) ? 13.80 ? 12.50 ? 10.00 ? 9.43 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), tsiz(0:1), reg , rsv , ptr high-z (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b11 clkout to ts , bb assertion (max = 0.25 b1 + 6.0) 7.60 13.60 6.30 12.30 3.80 9.80 3.13 9.13 ns b11a clkout to ta , bi assertion (when driven by the memory controller or pcmcia interface) (max = 0.00 b1 + 9.30 1 ) 2.50 9.30 2.50 9.30 2.50 9.80 2.5 9.3 ns b12 clkout to ts , bb negation (max = 0.25 b1 + 4.8) 7.60 12.30 6.30 11.00 3.80 8.50 3.13 7.92 ns b12a clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) (max = 0.00 b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.5 9.00 ns b13 clkout to ts , bb high-z (min = 0.25 b1) 7.60 21.60 6.30 20.30 3.80 14.00 3.13 12.93 ns b13a clkout to ta , bi high-z (when driven by the memory controller or pcmcia interface) (min = 0.00 b1 + 2.5) 2.50 15.00 2.50 15.00 2.50 15.00 2.5 15.00 ns b14 clkout to tea assertion (max = 0.00 b1 + 9.00) 2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 19 bus signal timing b15 clkout to tea high-z (min = 0.00 b1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns b16 ta , bi valid to clkout (setup time) (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6 ? ns b16a tea , kr , retry , cr valid to clkout (setup time) (min = 0.00 b1 + 4.5) 4.50 ? 4.50 ? 4.50 ? 4.50 ? ns b16b bb , bg , br , valid to clkout (setup time) 2 (4min = 0.00 b1 + 0.00) 4.00 ? 4.00 ? 4.00 ? 4.00 ? ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time) (min = 0.00 b1 + 1.00 3 ) 1.00 ? 1.00 ? 2.00 ? 2.00 ? ns b17a clkout to kr , retry , cr valid (hold time) (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b18 d(0:31) valid to clkout rising edge (setup time) 4 (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6.00 ? ns b19 clkout rising edge to d(0:31) valid (hold time) 4 (min = 0.00 b1 + 1.00 5 ) 1.00 ? 1.00 ? 2.00 ? 2.00 ? ns b20 d(0:31) valid to clkout falling edge (setup time) 6 (min = 0.00 b1 + 4.00) 4.00 ? 4.00 ? 4.00 ? 4.00 ? ns b21 clkout falling edge to d(0:31) valid (hold time) 6 (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b22 clkout rising edge to cs asserted gpcm acs = 00 (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b22a clkout falling edge to cs asserted gpcm acs = 10, trlx = 0 (max = 0.00 b1 + 8.00) ? 8.00 ? 8.00 ? 8.00 ? 8.00 ns b22b clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 0 (max = 0.25 b1 + 6.3) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.43 ns b22c clkout falling edge to cs asserted gpcm acs = 11, trlx = 0, ebdf = 1 (max = 0.375 b1 + 6.6) 10.90 18.00 10.90 16.00 5.20 12.30 4.69 10.93 ns b23 clkout rising edge to cs negated gpcm read access, gpcm write access acs = 00, trlx = 0 and csnt = 0 (max = 0.00 b1 + 8.00) 2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b24a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 20 freescale semiconductor bus signal timing b25 clkout rising edge to oe , we (0:3)/bs_b[0:3] asserted (max = 0.00 b1 + 9.00) ? 9.00 9.00 9.00 ? 9.00 ns b26 clkout rising edge to oe negated (max = 0.00 b1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 (min = 1.25 b1 ? 2.00) 35.90 ? 29.30 ? 16.90 ? 13.60 ? ns b27a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b28 clkout rising edge to we (0:3)/bs_b[0:3] negated gpcm write access csnt = 0 (max = 0.00 b1 + 9.00) ? 9.00 ? 9.00 ? 9.00 ? 9.00 ns b28a clkout falling edge to we (0:3)/bs_b[0:3] negated gpcm write access trlx = 0, csnt = 1, ebdf = 0 (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 9.93 ns b28b clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 0 (max = 0.25 b1 + 6.80) ? 14.30 ? 13.00 ? 10.50 ? 9.93 ns b28c clkout falling edge to we (0:3)/bs_b[0:3] negated gpcm write access trlx = 0, csnt = 1 write access trlx = 0, csnt = 1, ebdf = 1 (max = 0.375 b1 + 6.6) 10.90 18.00 10.90 18.00 5.20 12.30 4.69 11.29 ns b28d clkout falling edge to cs negated gpcm write access trlx = 0, csnt = 1, acs = 10 or acs = 11, ebdf = 1 (max = 0.375 b1 + 6.6) ? 18.00 ? 18.00 ? 12.30 ? 11.30 ns b29 we (0:3)/bs_b[0:3] negated to d(0:31) high-z gpcm write access, csnt = 0, ebdf = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b29a we (0:3)/bs_b[0:3] negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b29b cs negated to d(0:31) high-z gpcm write access, acs = 00, trlx = 0 and csnt = 0 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b29c cs negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, acs = 10 or acs = 11, ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 21 bus signal timing b29d we (0:3)/bs_b[0:3] negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b29e cs negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b29f we (0:3/bs_b[0:3]) negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1, ebdf = 1 (min = 0.375 b1?6.30) 7 5.00 ? 3.00 ? 0.00 ? 0.00 ? ns b29g cs negated to d(0:31) high-z gpcm write access, trlx = 0, csnt = 1 acs = 10 or acs = 11, ebdf = 1 (min = 0.375 b1 ? 6.30) 7 5.00 ? 3.00 ? 0.00 ? 0.00 ? ns b29h we (0:3)/bs_b[0:3] negated to d(0:31) high-z gpcm write access, trlx = 1, csnt = 1, ebdf = 1 (min = 0.375 b1?3.30) 38.40 ? 31.10 ? 17.50 ? 13.85 ? ns b29i cs negated to d(0:31) (0:3) high-z gpcm write access, trlx = 1, csnt = 1, acs = 10 or acs = 11, ebdf = 1 (min = 0.375 b1 ? 3.30) 38.40 ? 31.10 ? 17.50 ? 13.85 ? ns b30 cs , we (0:3)/bs_b[0:3] negated to a(0:31), baddr(28:30) invalid gpcm write access 8 (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b30a we (0:3)/bs_b[0:3] negated to a(0:31), baddr(28:30) invalid gpcm, write access, trlx = 0, csnt = 1, cs negated to a(0:31), invalid gpcm write access trlx = 0, csnt = 1, acs = 10 or acs == 11, ebdf = 0 (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b30b we (0:3)/bs_b[0:3] negated to a(0:31), invalid gpcm baddr(28:30), invalid gpcm write access, trlx = 1, csnt = 1. cs negated to a(0:31), invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or acs == 11, ebdf = 0 (min = 1.50 b1 ? 2.00) 43.50 ? 35.50 ? 20.70 ? 16.75 ? ns b30c we (0:3)/bs_b[0:3] negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx = 0, csnt = 1. cs negated to a(0:31) invalid gpcm write access, trlx = 0, csnt = 1 acs = 10 or acs == 11, ebdf = 1 (min = 0.375 b1 ? 3.00) 8.40 ? 6.40 ? 2.70 ? 1.70 ? ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 22 freescale semiconductor bus signal timing b30d we (0:3)/bs_b[0:3] negated to a(0:31), baddr(28:30) invalid gpcm write access trlx = 1, csnt =1, cs negated to a(0:31) invalid gpcm write access trlx = 1, csnt = 1, acs = 10 or 11, ebdf = 1 38.67 ? 31.38 ? 17.83 ? 14.19 ? ns b31 clkout falling edge to cs valid as requested by control bit cst4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b31a clkout falling edge to cs valid as requested by control bit cst1 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b31b clkout rising edge to cs valid, as requested by control bit cst2 in the corresponding word in the upm (max = 0.00 b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b31c clkout rising edge to cs valid, as requested by control bit cst3 in the corresponding word in the upm (max = 0.25 b1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns b31d clkout falling edge to cs valid as requested by control bit cst1 in the corresponding word in the upm ebdf = 1 (max = 0.375 b1 + 6.6) 13.30 18.00 11.30 16.00 7.60 12.30 4.69 11.30 ns b32 clkout falling edge to bs valid as requested by control bit bst4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns b32a clkout falling edge to bs valid as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b32b clkout rising edge to bs valid, as requested by control bit bst2 in the corresponding word in the upm (max = 0.00 b1 + 8.00) 1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns b32c clkout rising edge to bs valid, as requested by control bit bst3 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b32d clkout falling edge to bs valid as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 (max = 0.375 b1 + 6.60) 13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30 ns b33 clkout falling edge to gpl valid as requested by control bit gxt4 in the corresponding word in the upm (max = 0.00 b1 + 6.00) 1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 23 bus signal timing b33a clkout rising edge to gpl valid as requested by control bit gxt3 in the corresponding word in the upm (max = 0.25 b1 + 6.80) 7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b34a a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by control bit cst1 in the corresponding word in the upm (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b34b a(0:31), baddr(28:30), and d(0:31) to cs valid, as requested by cst2 in the corresponding word in upm (min = 0.75 b1 ? 2.00) 20.70 ? 16.70 ? 9.40 ? 6.80 ? ns b35 a(0:31), baddr(28:30) to cs valid as requested by control bit bst4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b35a a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by bst1 in the corresponding word in the upm (min = 0.50 b1 ? 2.00) 13.20 ? 10.50 ? 5.60 ? 4.25 ? ns b35b a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst2 in the corresponding word in the upm (min = 0.75 b1 ? 2.00) 20.70 ? 16.70 ? 9.40 ? 7.40 ? ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid as requested by control bit gxt4 in the corresponding word in the upm (min = 0.25 b1 ? 2.00) 5.60 ? 4.30 ? 1.80 ? 1.13 ? ns b37 upwait valid to clkout falling edge 9 (min = 0.00 b1 + 6.00) 6.00 ? 6.00 ? 6.00 ? 6.00 ? ns b38 clkout falling edge to upwait valid 9 (min = 0.00 b1 + 1.00) 1.00 ? 1.00 ? 1.00 ? 1.00 ? ns b39 as valid to clkout rising edge 10 (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns b40 a(0:31), tsiz(0:1), rd/wr , burst valid to clkout rising edge (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns b41 ts valid to clkout rising edge (setup time) (min = 0.00 b1 + 7.00) 7.00 ? 7.00 ? 7.00 ? 7.00 ? ns table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 24 freescale semiconductor bus signal timing b42 clkout rising edge to ts valid (hold time) (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns b43 as negation to memory controller signals negation (max = tbd) ? tbd ? tbd ? tbd ? tbd ns 1 for part speeds above 50 mhz, use 9.80 ns for b11a. 2 the timing required for br input is relevant when the mpc875/mpc870 is selected to work with the internal bus arbiter. the timing for bg input is relevant when the mpc875/mpc870 is selected to work with the external bus arbiter. 3 for part speeds above 50 mhz, use 2 ns for b17. 4 the d(0:31) input timings b18 and b19 refer to the rising edge of the clkout in which the ta input signal is asserted. 5 for part speeds above 50 mhz, use 2 ns for b19. 6 the d(0:31) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of the user-programmable machine (upm) in the memory controller, for data beats where dlt3 = 1 in the ram words. (this is only the case where data is latched on the falling edge of clkout.) 7 this formula applies to bus operation up to 50 mhz. 8 the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0. 9 the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings specified in b37 and b38 are specified to enable the freeze of the upm output signals as described in figure 20 . 10 the as signal is considered asynchronous to the clkout. the timing b39 is specified in order to allow the behavior specified in figure 23 . table 10. bus operation timings (continued) num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 25 bus signal timing figure 5 provides the control timing diagram. . figure 5. control timing figure 6 provides the timing for the external clock. figure 6. external clock timing clkout outputs a b outputs b a inputs d c inputs c d a maximum output delay specification. b minimum output hold time. c minimum input setup time specification. d minimum input hold time specification. clkout b1 b5 b3 b4 b1 b2
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 26 freescale semiconductor bus signal timing figure 7 provides the timing for the synchronous output signals. figure 7. synchronous output signals timing figure 8 provides the timing for the synchronous ac tive pull-up and open-drain output signals. figure 8. synchronous active pull-up resistor and open-drain outputs signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb ta , bi tea b13 b12 b11 b11 b12a b13a b15 b14
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 27 bus signal timing figure 9 provides the timing for the synchronous input signals. figure 9. synchronous input signals timing figure 10 provides normal case timing for input data. it also applies to normal read accesses under the control of the user-programmable machine (upm) in the memory controller. figure 10. input data timing in normal case clkout ta , bi tea , kr , retry , cr bb , bg , br b16 b17 b16a b17a b16b b17 clkout ta d[0:31] b16 b17 b19 b18
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 28 freescale semiconductor bus signal timing figure 11 provides the timing for the input data controlled by the upm for data beats where dlt3 = 1 in the upm ram words. (this is only the case where data is latched on the falling edge of clkout.) figure 11. input data timing when controlled by upm in the memory controller and dlt3 = 1 figure 12 through figure 15 provide the timing for the external bus read controlled by various gpcm factors. figure 12. external bus read timing (gpcm controlled?acs = 00) clkout ta d[0:31] b20 b21 clkout a[0:31] csx oe we [0:3] ts d[0:31] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 29 bus signal timing figure 13. external bus read timing (gpcm controlled?trlx = 0, acs = 10) figure 14. external bus read timing (gpcm controlled?trlx = 0, acs = 11) clkout a[0:31] cs x oe ts d[0:31] b11 b12 b8 b22a b23 b26 b19 b18 b25 b24 clkout a[0:31] cs x oe ts d[0:31] b11 b12 b22b b8 b22c b23 b24a b25 b26 b19 b18
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 30 freescale semiconductor bus signal timing figure 15. external bus read timing (gpcm controlled?trlx = 1, acs = 10, acs = 11) clkout a[0:31] cs x oe ts d[0:31] b11 b12 b8 b22a b27 b27a b22b b22c b19 b18 b26 b23
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 31 bus signal timing figure 16 through figure 18 provide the timing for the external bus write controlled by various gpcm factors. figure 16. external bus write timing (gpcm controlled?trlx = 0, csnt = 0) clkout a[0:31] cs x we [0:3] oe ts d[0:31] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29 b29b
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 32 freescale semiconductor bus signal timing figure 17. external bus write timing (gpcm controlled?trlx = 0, csnt = 1) b23 b30a b30c clkout a[0:31] cs x oe we [0:3] ts d[0:31] b11 b8 b22 b12 b28b b28d b25 b26 b8 b28a b9 b28c b29c b29g b29a b29f
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 33 bus signal timing figure 18. external bus write timing (gpcm controlled?trlx = 1, csnt = 1) b23 b22 b8 b12 b11 clkout a[0:31] cs x we [0:3] ts oe d[0:31] b30d b30b b28b b28d b25 b29e b29i b26 b29d b29h b28a b28c b9 b8 b29b
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 34 freescale semiconductor bus signal timing figure 19 provides the timing for the external bus controlled by the upm. figure 19. external bus timing (upm controlled signals) clkout cs x b31d b8 b31 b34 b32b gpl_a [0:5], gpl_b [0:5] bs_a [0:3] a[0:31] b31c b31b b34a b32 b32a b32d b34b b36 b35b b35a b35 b33 b32c b33a b31a
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 35 bus signal timing figure 20 provides the timing for the asynchronous asserted upwait signal controlled by the upm. figure 20. asynchronous upwait asserted detection in upm handled cycles timing figure 21 provides the timing for the asynchronous nega ted upwait signal controlled by the upm. figure 21. asynchronous upwait negated detection in upm handled cycles timing clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3] b37 b38 clkout cs x upwait gpl_a [0:5], gpl_b [0:5] bs_a [0:3] b37 b38
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 36 freescale semiconductor bus signal timing figure 22 provides the timing for the synchronous external master access controlled by the gpcm. figure 22. synchronous external master access timing (gpcm handled acs = 00) figure 23 provides the timing for the asynchronous external master memory access controlled by the gpcm. figure 23. asynchronous external master memory access timing (gpcm controlled?acs = 00) figure 24 provides the timing for the asynchronous external master control signals negation. figure 24. asynchronous external master?control signals negation timing clkout ts a[0:31], tsiz[0:1], r/w , burst cs x b41 b42 b40 b22 clkout as a[0:31], tsiz[0:1], r/w cs x b39 b40 b22 as cs x, we [0:3], oe , gplx , bs [0:3] b43
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 37 bus signal timing table 11 provides the interrupt timing for the mpc875/mpc870. figure 25 provides the interrupt detection timing for the external level-sensitive lines. figure 25. interrupt detection timing for external level sensitive lines figure 26 provides the interrupt detection timing for the external edge-sensitive lines. figure 26. interrupt detection timing for external edge-sensitive lines table 11. interrupt timing num characteristic 1 1 the i39 and i40 timings describe the testing conditions under which the irq lines are tested when being defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the i41, i42, and i43 timings are specified to allow correct functioning of the irq lines detection circuitry and have no direct relation with the total system interrupt latency that the mpc875/mpc870 is able to support. all frequencies unit min max i39 irq x valid to clkout rising edge (setup time) 6.00 ns i40 irq x hold time after clkout 2.00 ns i41 irq x pulse width low 3.00 ns i42 irq x pulse width high 3.00 ns i43 irq x edge-to-edge time 4 t clockout ? clkout irq x i39 i40 clkout irq x i41 i42 i43 i43
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 38 freescale semiconductor bus signal timing table 12 shows the pcmcia timing for the mpc875/mpc870. table 12. pcmcia timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max p44 a(0:31), reg valid to pcmcia strobe asserted 1 (min = 0.75 b1 ? 2.00) 1 psst = 1. otherwise add psst times cycle time. psht = 0. otherwise add psht times cycle time. these synchronous timings define when the waita signals are detected in order to freeze (or relieve) the pcmcia current cycle. the waita assertion will be effective only if it is detected 2 cycles before the psl timer expiration. see chapter 16, ?pcmcia interface,? in the mpc885 powerquicc? family reference manual . 20.70 ? 16.70 ? 9.40 ? 7.40 ? ns p45 a(0:31), reg valid to ale negation 1 (min = 1.00 b1 ? 2.00) 28.30 ? 23.00 ? 13.20 ? 10.50 ? ns p46 clkout to reg valid (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p47 clkout to reg invalid (min = 0.25 b1 + 1.00) 8.60 ? 7.30 ? 4.80 ? 4.125 ? ns p48 clkout to ce1 , ce2 asserted (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p49 clkout to ce1 , ce2 negated (max = 0.25 b1 + 8.00) 7.60 15.60 6.30 14.30 3.80 11.80 3.13 11.13 ns p50 clkout to pcoe , iord , pcwe , iowr assert time (max = 0.00 b1 + 11.00) ? 11.00 ? 11.00 ? 11.00 ? 11.00 ns p51 clkout to pcoe , iord , pcwe , iowr negate time (max = 0.00 b1 + 11.00) 2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns p52 clkout to ale assert time (max = 0.25 b1 + 6.30) 7.60 13.80 6.30 12.50 3.80 10.00 3.13 9.40 ns p53 clkout to ale negate time (max = 0.25 b1 + 8.00) ? 15.60 ? 14.30 ? 11.80 ? 11.13 ns p54 pcwe , iowr negated to d(0:31) invalid 1 (min = 0.25 b1?2.00) 5.60 ? 4.30 ? 1.80 ? 1.125 ? ns p55 waita and waitb valid to clkout rising edge 1 (min = 0.00 b1 + 8.00) 8.00 ? 8.00 ? 8.00 ? 8.00 ? ns p56 clkout rising edge to waita and waitb invalid 1 (min = 0.00 b1 + 2.00) 2.00 ? 2.00 ? 2.00 ? 2.00 ? ns
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 39 bus signal timing figure 27 provides the pcmcia access cycle timing for the external bus read. figure 27. pcmcia access cycles timing external bus read clkout a[0:31] reg ce1 /ce2 pcoe , iord ts d[0:31] ale b19 b18 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 40 freescale semiconductor bus signal timing figure 28 provides the pcmcia access cycle timing for the external bus write. figure 28. pcmcia access cycles timing external bus write figure 29 provides the pcmcia wait signals detection timing. figure 29. pcmcia wait signals detection timing clkout a[0:31] reg ce1 /ce2 pcwe , iowr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout wait a p55 p56
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 41 bus signal timing table 13 shows the pcmcia port timing for the mpc875/mpc870. figure 30 provides the pcmcia output port timing for the mpc875/mpc870. figure 30. pcmcia output port timing figure 31 provides the pcmcia input port timing for the mpc875/mpc870. figure 31. pcmcia input port timing table 13. pcmcia port timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max p57 clkout to opx valid (max = 0.00 b1 + 19.00) ? 19.00 ? 19.00 ? 19.00 ? 19.00 ns p58 hreset negated to opx drive 1 (min = 0.75 b1 + 3.00) 1 op2 and op3 only. 25.70 ? 21.70 ? 14.40 ? 12.40 ? ns p59 ip_xx valid to clkout rising edge (min = 0.00 b1 + 5.00) 5.00 ? 5.00 ? 5.00 ? 5.00 ? ns p60 clkout rising edge to ip_xx invalid (min = 0.00 b1 + 1.00) 1.00 ? 1.00 ? 1.00 ? 1.00 ? ns clkout hreset output signals op2, op3 p57 p58 clkout input signals p59 p60
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 42 freescale semiconductor bus signal timing table 14 shows the debug port timing for the mpc875/mpc870. figure 32 provides the input timing for the debug port clock. figure 32. debug port clock input timing figure 33 provides the timing for the debug port. figure 33. debug port timings table 14. debug port timing num characteristic all frequencies unit min max d61 dsck cycle time 3 t clockout ? d62 dsck clock pulse width 1.25 t clockout ? d63 dsck rise and fall times 0.00 3.00 ns d64 dsdi input data setup time 8.00 ns d65 dsdi data hold time 5.00 ns d66 dsck low to dsdo data valid 0.00 15.00 ns d67 dsck low to dsdo invalid 0.00 2.00 ns dsck d61 d61 d63 d62 d62 d63 dsck dsdi dsdo d64 d65 d66 d67
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 43 bus signal timing table 15 shows the reset timing for the mpc875/mpc870. table 15. reset timing num characteristic 33 mhz 40 mhz 66 mhz 80 mhz unit min max min max min max min max r69 clkout to hreset high impedance (max = 0.00 b1 + 20.00) ? 20.00 ? 20.00 ? 20.00 ? 20.00 ns r70 clkout to sreset high impedance (max = 0.00 b1 + 20.00) ? 20.00 ? 20.00 ? 20.00 ? 20.00 ns r71 rstconf pulse width (min = 17.00 b1) 515.20 ? 425.00 ? 257.60 ? 212.50 ? ns r72 ? ????????? r73 configuration data to hreset rising edge setup time (min = 15.00 b1 + 50.00) 504.50 ? 425.00 ? 277.30 ? 237.50 ? ns r74 configuration data to rstconf rising edge setup time (min = 0.00 b1 + 350.00) 350.00 ? 350.00 ? 350.00 ? 350.00 ? ns r75 configuration data hold time after rstconf negation (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r76 configuration data hold time after hreset negation (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r77 hreset and rstconf asserted to data out drive (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r78 rstconf negated to data out high impedance (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r79 clkout of last rising edge before chip three-states hreset to data out high impedance (max = 0.00 b1 + 25.00) ? 25.00 ? 25.00 ? 25.00 ? 25.00 ns r80 dsdi, dsck setup (min = 3.00 b1) 90.90 ? 75.00 ? 45.50 ? 37.50 ? ns r81 dsdi, dsck hold time (min = 0.00 b1 + 0.00) 0.00 ? 0.00 ? 0.00 ? 0.00 ? ns r82 sreset negated to clkout rising edge for dsdi and dsck sample (min = 8.00 b1) 242.40 ? 200.00 ? 121.20 ? 100.00 ? ns
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 44 freescale semiconductor bus signal timing figure 34 shows the reset timing for the data bus configuration. figure 34. reset timing?configuration from data bus figure 35 provides the reset timing for the data bus weak drive dur ing configuration. figure 35. reset timing?data bus weak drive during configuration figure 36 provides the reset timing for the debug port configuration. figure 36. reset timing?debug port configuration hreset rstconf d[0:31] (in) r71 r74 r73 r75 r76 clkout hreset d[0:31] (out) (weak) rstconf r69 r79 r77 r78 clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 45 ieee 1149.1 electrical specifications 12 ieee 1149.1 electrical specifications table 16 provides the jtag timings for the mpc875/mpc870 shown in figure 37 through figure 40 . figure 37. jtag test clock input timing table 16. jtag timing num characteristic all frequencies unit min max j82 tck cycle time 100.00 ? ns j83 tck clock pulse width measured at 1.5 v 40.00 ? ns j84 tck rise and fall times 0.00 10.00 ns j85 tms, tdi data setup time 5.00 ? ns j86 tms, tdi data hold time 25.00 ? ns j87 tck low to tdo data valid ? 27.00 ns j88 tck low to tdo data invalid 0.00 ? ns j89 tck low to tdo high impedance ? 20.00 ns j90 trst assert time 100.00 ? ns j91 trst setup time to tck low 40.00 ? ns j92 tck falling edge to output valid ? 50.00 ns j93 tck falling edge to output valid out of high impedance ? 50.00 ns j94 tck falling edge to output high impedance ? 50.00 ns j95 boundary scan input valid to tck rising edge 50.00 ? ns j96 tck rising edge to boundary scan input invalid 50.00 ? ns tck j82 j83 j82 j83 j84 j84
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 46 freescale semiconductor ieee 1149.1 electrical specifications figure 38. jtag test access port timing diagram figure 39. jtag trst timing diagram figure 40. boundary scan (jtag) timing diagram tck tms, tdi tdo j85 j86 j87 j88 j89 tck trst j91 j90 tck output signals output signals output signals j92 j94 j93 j95 j96
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 47 cpm electrical characteristics 13 cpm electrical characteristics this section provides the ac and dc electrical sp ecifications for the communi cations processor module (cpm) of the mpc875/mpc870. 13.1 port c interrupt ac electrical specifications table 17 provides the timings for port c interrupts. figure 41 shows the port c interrupt detection timing. figure 41. port c interrupt detection timing 13.2 idma controller ac electrical specifications table 18 provides the idma controller timings as shown in figure 42 through figure 45 . table 17. port c interrupt timing num characteristic 33.34 mhz unit min max 35 port c interrupt pulse width low (edge-triggered mode) 55 ? ns 36 port c interrupt minimum time between active edges 55 ? ns table 18. idma controller timing num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 ? ns 41 dreq hold time from clock high 1 1 applies to high-to-low mode (edm = 1). tbd ? ns 42 sdack assertion delay from clock high ? 12 ns 43 sdack negation delay from clock low ? 12 ns 44 sdack negation delay from ta low ? 20 ns 45 sdack negation delay from clock high ? 15 ns 46 ta assertion to rising edge of the clock setup time (applies to external ta )7?n s port c 35 36 (input)
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 48 freescale semiconductor cpm electrical characteristics figure 42. idma external requests timing diagram figure 43. sdack timing diagram?peripheral write, externally-generated ta 41 40 dreq (input) clko (output) data 42 46 43 clko (output) ts (output) r/w (output) sdack ta (input)
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 49 cpm electrical characteristics figure 44. sdack timing diagram?peripheral write, internally-generated ta figure 45. sdack timing diagram?peripheral read, internally-generated ta data 42 44 clko (output) ts (output) r/w (output) ta (output) sdack data 42 45 clko (output) ts (output) r/w (output) ta (output) sdack
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 50 freescale semiconductor cpm electrical characteristics 13.3 baud rate generator ac electrical specifications table 19 provides the baud rate generator timings as shown in figure 46 . figure 46. baud rate generator timing diagram 13.4 timer ac electrical specifications table 20 provides the general-purpose timer timings as shown in figure 47 . table 19. baud rate generator timing num characteristic all frequencies unit min max 50 brgo rise and fall time ? 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 ? ns table 20. timer timing num characteristic all frequencies unit min max 61 tin/tgate rise and fall time 10 ? ns 62 tin/tgate low time 1 ? clk 63 tin/tgate high time 2 ? clk 64 tin/tgate cycle time 3 ? clk 65 clko low to tout valid 3 25 ns 52 50 51 brgox 50 51
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 51 cpm electrical characteristics figure 47. cpm general-purpose timers timing diagram 13.5 serial interface ac electrical specifications table 21 provides the serial interface (si) timings as shown in figure 48 through figure 52 . table 21. si timing num characteristic all frequencies unit min max 70 l1rclkb, l1tclkb frequency (dsc = 0) 1, 2 ? syncclk/2.5 mhz 71 l1rclkb, l1tclkb width low (dsc = 0) 2 p + 10 ? ns 71a l1rclkb, l1tclkb width high (dsc = 0) 3 p + 10 ? ns 72 l1txdb, l1st1 and l1st2, l1rq , l1clko rise/fall time ? 15.00 ns 73 l1rsyncb, l1tsyncb valid to l1clkb edge (sync setup time) 20.00 ? ns 74 l1clkb edge to l1rsyncb, l1tsyncb, invalid (sync hold time) 35.00 ? ns 75 l1rsyncb, l1tsyncb rise/fall time ? 15.00 ns 76 l1rxdb valid to l1clkb edge (l1rxdb setup time) 17.00 ? ns 77 l1clkb edge to l1rxdb invalid (l1rxdb hold time) 13.00 ? ns 78 l1clkb edge to l1st1 and l1st2 valid 4 10.00 45.00 ns 78a l1syncb valid to l1st1 and l1st2 valid 10.00 45.00 ns 79 l1clkb edge to l1st1 and l1st2 invalid 10.00 45.00 ns 80 l1clkb edge to l1txdb valid 10.00 55.00 ns 80a l1tsyncb valid to l1txdb valid 4 10.00 55.00 ns 81 l1clkb edge to l1txdb high impedance 0.00 42.00 ns 82 l1rclkb, l1tclkb frequency (dsc = 1) ? 16.00 or syncclk/2 mhz 83 l1rclkb, l1tclkb width low (dsc = 1) p + 10 ? ns clko tin/tgate (input) tout (output) 64 65 61 62 63 61 60
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 52 freescale semiconductor cpm electrical characteristics figure 48. si receive timing diagram with normal clocking (dsc = 0) 83a l1rclkb, l1tclkb width high (dsc = 1) 3 p + 10 ? ns 84 l1clkb edge to l1clkob valid (dsc = 1) ? 30.00 ns 85 l1rqb valid before falling edge of l1tsyncb 4 1.00 ? l1tclk 86 l1grb setup time 2 42.00 ? ns 87 l1grb hold time 42.00 ? ns 88 l1clkb edge to l1syncb valid (fsd = 00) cnt = 0000, byt = 0, dsc = 0) ?0 . 0 0n s 1 the ratio syncclk/l1rclkb must be greater than 2.5/1. 2 these specs are valid for idl mode only. 3 where p = 1/clkout. thus, for a 25-mhz clko1 rate, p = 40 ns. 4 these strobes and txd on the first bit of the frame become valid after the l1clkb edge or l1syncb, whichever comes later. table 21. si timing (continued) num characteristic all frequencies unit min max l1rxdb (input) l1rclkb (fe = 0, ce = 0) (input) l1rclkb (fe = 1, ce = 1) (input) l1rsyncb (input) l1st(2?1) (output) 71 72 70 71a rfsd=1 75 73 74 77 78 76 79 bit0
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 53 cpm electrical characteristics figure 49. si receive timing with double-speed clocking (dsc = 1) l1rxdb (input) l1rclkb (fe = 1, ce = 1) (input) l1rclkb (fe = 0, ce = 0) (input) l1rsyncb (input) l1st(2?1) (output) 72 rfsd=1 75 73 74 77 78 76 79 83a 82 l1clkob (output) 84 bit0
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 54 freescale semiconductor cpm electrical characteristics figure 50. si transmit timing diagram (dsc = 0) l1txdb (output) l1tclkb (fe = 0, ce = 0) (input) l1tclkb (fe = 1, ce = 1) (input) l1tsyncb (input) l1st(2?1) (output) 71 70 72 73 75 74 80a 80 78 tfsd=0 81 79 bit0
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 55 cpm electrical characteristics figure 51. si transmit timing with double speed clocking (dsc = 1) l1txdb (output) l1rclkb (fe = 0, ce = 0) (input) l1rclkb (fe = 1, ce = 1) (input) l1rsyncb (input) l1st(2?1) (output) 72 tfsd=0 75 73 74 78a 80 79 83a 82 l1clkob (output) 84 bit0 78 81
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 56 freescale semiconductor cpm electrical characteristics figure 52. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxdb (input) l1txdb (output) l1st(2?1) (output) l1rqb (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1grb (input) 78 85 72 76 87 86 l1rsyncb (input) l1rclkb (input) 81
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 57 cpm electrical characteristics 13.6 scc in nmsi mode electrical specifications table 22 provides the nmsi external clock timing. table 23 provides the nmsi internal clock timing. table 22. nmsi external clock timing num characteristic all frequencies unit min max 100 rclk3 and tclk3 width high 1 1 the ratios syncclk/rclk3 and syncclk/tclk3 must be greater than or equal to 2.25/1. 1/syncclk ? ns 101 rclk3 and tclk3 width low 1/syncclk + 5 ? ns 102 rclk3 and tclk3 rise/fall time ? 15.00 ns 103 txd3 active delay (from tclk3 falling edge) 0.00 50.00 ns 104 rts3 active/inactive delay (from tclk3 falling edge) 0.00 50.00 ns 105 cts3 setup time to tclk3 rising edge 5.00 ? ns 106 rxd3 setup time to rclk3 rising edge 5.00 ? ns 107 rxd3 hold time from rclk3 rising edge 2 2 also applies to cd and cts hold time when they are used as external sync signals. 5.00 ? ns 108 cd3 setup time to rclk3 rising edge 5.00 ? ns table 23. nmsi internal clock timing num characteristic all frequencies unit min max 100 rclk3 and tclk3 frequency 1 1 the ratios syncclk/rclk3 and syncclk/tclk3 must be greater or equal to 3/1. 0.00 syncclk/3 mhz 102 rclk3 and tclk3 rise/fall time ? ? ns 103 txd3 active delay (from tclk3 falling edge) 0.00 30.00 ns 104 rts3 active/inactive delay (from tclk3 falling edge) 0.00 30.00 ns 105 cts3 setup time to tclk3 rising edge 40.00 ? ns 106 rxd3 setup time to rclk3 rising edge 40.00 ? ns 107 rxd3 hold time from rclk3 rising edge 2 2 also applies to cd and cts hold time when they are used as external sync signals. 0.00 ? ns 108 cd3 setup time to rclk3 rising edge 40.00 ? ns
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 58 freescale semiconductor cpm electrical characteristics figure 53 through figure 55 show the nmsi timings. figure 53. scc nmsi receive timing diagram figure 54. scc nmsi transmit timing diagram rclk3 cd3 (input) 102 100 107 108 107 rxd3 (input) cd3 (sync input) 102 101 106 tclk3 cts3 (input) 102 100 104 107 txd3 (output) cts3 (sync input) 102 101 rts3 (output) 105 103 104
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 59 cpm electrical characteristics figure 55. hdlc bus timing diagram 13.7 ethernet electrical specifications table 24 provides the ethernet timings as shown in figure 56 through figure 58 . table 24. ethernet timing num characteristic all frequencies unit min max 120 clsn width high 40 ? ns 121 rclk3 rise/fall time ? 15 ns 122 rclk3 width low 40 ? ns 123 rclk3 clock period 1 80 120 ns 124 rxd3 setup time 20 ? ns 125 rxd3 hold time 5?ns 126 rena active delay (from rclk3 rising edge of the last data bit) 10 ? ns 127 rena width low 100 ? ns 128 tclk3 rise/fall time ? 15 ns 129 tclk3 width low 40 ? ns 130 tclk3 clock period 1 99 101 ns 131 txd3 active delay (from tclk3 rising edge) ? 50 ns 132 txd3 inactive delay (from tclk3 rising edge) 6.5 50 ns 133 tena active delay (from tclk3 rising edge) 10 50 ns 134 tena inactive delay (from tclk3 rising edge) 10 50 ns tclk3 cts3 (echo input) 102 100 104 txd3 (output) 102 101 rts3 (output) 103 104 107 105
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 60 freescale semiconductor cpm electrical characteristics figure 56. ethernet collision timing diagram figure 57. ethernet receive timing diagram 138 clko1 low to sdack asserted 2 ?20ns 139 clko1 low to sdack negated 2 ?20ns 1 the ratios syncclk/rclk3 and syncclk/tclk3 must be greater than or equal to 2/1. 2 sdack is asserted whenever the sdma writes the incoming frame da into memory. table 24. ethernet timing (continued) num characteristic all frequencies unit min max clsn(cts1 ) 120 (input) rclk3 121 rxd3 (input) 121 rena(cd3 ) (input) 125 124 123 127 126 last bit
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 61 cpm electrical characteristics figure 58. ethernet transmit timing diagram 13.8 smc transparent ac electrical specifications table 25 provides the smc transparent timings as shown in figure 59 . table 25. smc transparent timing num characteristic all frequencies unit min max 150 smclk clock period 1 1 syncclk must be at least twice as fast as smclk. 100 ? ns 151 smclk width low 50 ? ns 151a smclk width high 50 ? ns 152 smclk rise/fall time ? 15 ns 153 smtxd active delay (from smclk falling edge) 10 50 ns 154 smrxd/smsync setup time 20 ? ns 155 rxd1/smsync hold time 5 ? ns tclk3 128 txd3 (output) 128 tena(rts3 ) (input) notes: transmit clock invert (tci) bit in gsmr is set. if rena is negated before tena or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 1. 2. rena(cd3 ) (input) 133 134 132 131 121 129 (note 2)
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 62 freescale semiconductor cpm electrical characteristics figure 59. smc transparent timing diagram 13.9 spi master ac electrical specifications table 26 provides the spi master timings as shown in figure 60 and figure 61 . table 26. spi master timing num characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 15 ? ns 163 master data hold time (inputs) 0 ? ns 164 master data valid (after sck edge) ? 10 ns 165 master data hold time (outputs) 0 ? ns 166 rise time output ? 15 ns 167 fall time output ?15ns smclk smrxd (input) 152 150 smtxd (output) 152 151 smsync 151 154 153 155 154 155 note 1 note: this delay is equal to an integer number of character-length clocks. 1.
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 63 cpm electrical characteristics figure 60. spi master (cp = 0) timing diagram figure 61. spi master (cp = 1) timing diagram spimosi (output) spiclk (ci = 0) (output) spiclk (ci = 1) (output) spimiso (input) 162 data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 spimosi (output) spiclk (ci = 0) (output) spiclk (ci = 1) (output) spimiso (input) data 166 167 161 161 160 msb lsb msb msb data lsb msb 167 166 163 166 167 165 164 162
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 64 freescale semiconductor cpm electrical characteristics 13.10 spi slave ac electrical specifications table 27 provides the spi slave timings as shown in figure 62 and figure 63 . figure 62. spi slave (cp = 0) timing diagram table 27. spi slave timing num characteristic all frequencies unit min max 170 slave cycle time 2?t cyc 171 slave enable lead time 15 ? ns 172 slave enable lag time 15 ? ns 173 slave clock (spiclk) high or low time 1 ? t cyc 174 slave sequential transfer delay (does not require deselect) 1 ? t cyc 175 slave data setup time (inputs) 20 ? ns 176 slave data hold time (inputs) 20 ? ns 177 slave access time ? 50 ns spimosi (input) spiclk (ci = 0) (input) spiclk (ci = 1) (input) spimiso (output) 180 data 181 182 173 173 170 msb lsb msb 181 177 182 175 179 spisel (input) 171 172 174 data msb lsb msb undef 181 178 176 182
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 65 cpm electrical characteristics figure 63. spi slave (cp = 1) timing diagram 13.11 i 2 c ac electrical specifications table 28 provides the i 2 c (scl < 100 khz) timings. table 28. i 2 c timing (scl < 100 kh z ) num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) 1 1.5 100 khz 202 bus free time between transmissions 4.7 ? s 203 low period of scl 4.7 ? s 204 high period of scl 4.0 ? s 205 start condition setup time 4.7 ? s 206 start condition hold time 4.0 ? s 207 data hold time 0? s 208 data setup time 250 ? ns 209 sdl/scl rise time ? 1 s spimosi (input) spiclk (ci = 0) (input) spiclk (ci = 1) (input) spimiso (output) 180 data 181 182 msb lsb 181 177 182 175 179 spisel (input) 174 data msb lsb undef 178 176 182 msb msb 172 173 173 171 170 181
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 66 freescale semiconductor cpm electrical characteristics table 29 provides the i 2 c (scl > 100 khz) timings. figure 64 shows the i 2 c bus timing. figure 64. i 2 c bus timing diagram 210 sdl/scl fall time ? 300 ns 211 stop condition setup time 4.7 ? s 1 scl frequency is given by scl = brgclk_frequency/((brg register + 3) pre_scalar 2). the ratio syncclk/(brgclk/pre_scalar) must be greater than or equal to 4/1. table 29. i 2 c timing (scl > 100 kh z ) num characteristic expression all frequencies unit min max 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) 1 1 scl frequency is given by scl = brgclk_frequency/((brg register + 3) pre_scalar 2). the ratio syncclk/(brgclk/pre_scalar) must be greater than or equal to 4/1. fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions ? 1/(2.2 fscl) ? s 203 low period of scl ? 1/(2.2 fscl) ? s 204 high period of scl ? 1/(2.2 fscl) ? s 205 start condition setup time ? 1/(2.2 fscl) ? s 206 start condition hold time ? 1/(2.2 fscl) ? s 207 data hold time ? 0 ? s 208 data setup time ? 1/(40 fscl) ? s 209 sdl/scl rise time ? ? 1/(10 fscl) s 210 sdl/scl fall time ? ? 1/(33 fscl) s 211 stop condition setup time ? 1/2(2.2 fscl) ? s table 28. i 2 c timing (scl < 100 kh z ) (continued) num characteristic all frequencies unit min max scl 202 205 203 207 204 208 206 209 211 210 sda
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 67 usb electrical characteristics 14 usb electrical characteristics this section provides the ac timings for the usb interface. 14.1 usb interface ac timing specifications the usb port uses the transmit clock on scc1. table 30 lists the usb interface timings. 15 fec electrical characteristics this section provides the ac electrical specifications for the fast ethernet controller (fec). note that the timing specifications for the mii signals are i ndependent of system clock frequency (part speed designation). also, mii signals use tt l signal levels compatible with de vices operating at either 5.0 or 3.3 v. 15.1 mii and reduced mii receive signal timing the receiver functions correctly up to a mii_rx_clk maximum frequency of 25 mhz + 1%. the reduced mii (rmii) receiver functions correctly up to a rmii_refclk maximum frequency of 50 mhz + 1%. there is no minimum frequency requirement. in addition, the processor clock frequency must exceed the mii_rx_clk frequency ? 1%. table 31 provides information on the mii receive signal timing. table 30. usb interface ac timing specifications name characteristic all frequencies unit min max us1 usbclk frequency of operation 1 low speed full speed 1 usbclk accuracy should be 500 ppm or better. usbclk may be stopped to conserve power. 6 48 mhz us4 usbclk duty cycle (measured at 1.5 v) 45 55 % table 31. mii receive signal timing num characteristic min max unit m1 mii_rxd[3:0], mii_rx_dv, mii_rx_er to mii_rx_clk setup 5 ? ns m2 mii_rx_clk to mii_rxd[3:0], mii_rx_dv, mii_rx_er hold 5 ? ns m3 mii_rx_clk pulse width high 35% 65% mii_rx_clk period m4 mii_rx_clk pulse width low 35% 65% mii_rx_clk period m1_rmii rmii_rxd[1:0], rmii_crs_dv, rmii_rx_err to rmii_refclk setup 4? ns m2_rmii rmii_refclk to rmii_rxd[1:0], rmii_crs_dv, rmii_rx_err hold 2? ns
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 68 freescale semiconductor fec electrical characteristics figure 65 shows mii receive signal timing. figure 65. mii receive signal timing diagram 15.2 mii and reduced mii transmit signal timing the transmitter functions correctly up to a mii_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, th e processor clock frequency must exceed the mii_tx_clk frequency ? 1%. table 32 provides information on the mii transmit signal timing. table 32. mii transmit signal timing num characteristic min max unit m5 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er invalid 5 ? ns m6 mii_tx_clk to mii_txd[3:0], mii_tx_en, mii_tx_er valid ? 25 ns m7 mii_tx_clk pulse width high 35% 65% mii_tx_clk period m8 mii_tx_clk pulse width low 35% 65% mii_tx_clk period m20_rmii rmii_txd[1:0], rmii_tx_en to rmii_refclk setup 4 ? ns m21_rmii rmii_txd[1:0], rmii_tx_en data hold from rmii_refclk rising edge 2? ns m1 m2 mii_rx_clk (input) mii_rxd[3:0] (inputs) mii_rx_dv mii_rx_er m3 m4
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 69 fec electrical characteristics figure 66 shows the mii transmit signal timing diagram. figure 66. mii transmit signal timing diagram 15.3 mii async inputs signal timing (mii_crs, mii_col) table 33 provides information on the mii async inputs signal timing. figure 67 shows the mii asynchronous inputs signal timing diagram. figure 67. mii async inputs timing diagram 15.4 mii serial management channel timing (mii_mdio, mii_mdc) table 34 provides information on the mii serial manage ment channel signal timing. the fec functions correctly with a maximum mdc frequency in excess of 2.5 mhz. table 33. mii async inputs signal timing num characteristic min max unit m9 mii_crs, mii_col minimum pulse width 1.5 ? mii_tx_clk period table 34. mii serial management channel timing num characteristic min max unit m10 mii_mdc falling edge to mii_mdio output invalid (minimum propagation delay) 0? ns m11 mii_mdc falling edge to mii_mdio output valid (max prop delay) ? 25 ns m12 mii_mdio (input) to mii_mdc rising edge setup 10 ? ns m13 mii_mdio (input) to mii_mdc rising edge hold 0 ? ns m14 mii_mdc pulse width high 40% 60% mii_mdc period m15 mii_mdc pulse width low 40% 60% mii_mdc period m6 mii_tx_clk (input) mii_txd[3:0] (outputs) mii_tx_en mii_tx_er m5 m7 m8 mii_crs, mii_col m9
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 70 freescale semiconductor fec electrical characteristics figure 68 shows the mii serial management channel timing diagram. figure 68. mii serial management channel timing diagram m11 mii_mdc (output) mii_mdio (output) m12 m13 mii_mdio (input) m10 m14 mm15
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 71 mechanical data and ordering information 16 mechanical data and ordering information table 35 identifies the packages and operating fr equencies available for the mpc875/mpc870. table 35. available mpc875/mpc870 packages/frequencies package type temperature (t j ) frequency (mhz) order number plastic ball grid array zt suffix?leaded vr suffix?lead-free are available as needed 0 c to 95 c 66 kmpc875zt66 kmpc870zt66 mpc875zt66 mpc870zt66 80 kmpc875zt80 kmpc870zt80 mpc875zt80 mpc870zt80 133 kmpc875zt133 kmpc870zt133 mpc875zt133 mpc870zt133 plastic ball grid array czt suffix?leaded cvr suffix?lead-free are available as needed -40 c to 100 c 66 kmpc875czt66 kmpc870czt66 mpc875czt66 mpc870czt66 133 kmpc875czt133 kmpc870czt133 mpc875czt133 mpc870czt133
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 72 freescale semiconductor mechanical data and ordering information 16.1 pin assignments figure 69 shows the jedec pinout of the pbga package as viewed from the top surface. for additional information, see the mpc885 powerquicc family user?s manual . note the pin numbering starts with b2 in order to conform to the jedec standard for 23-mm body size using a 16 16 array. note: this is the top view of the device. figure 69. pinout of the pbga package ? jedec standard modck2 ipa7 ipa4 d31 d29 d7 d18 d5 d3 d11 d10 n/c extclk modck1 op0 alea ipb0 burst irq6 br tea bi cs0 cs3 cs5 n/c rstconf sreset baddr29 op1 xtal ipa2 waita poreset extal baddr30 ipb1 bg gpla4 gpla5 wr ce2a cs7 we2 ipa5 ipa3 vddsyn as aleb irq2 bb hreset baddr28 irq3 d30 ipa6 ts ta bdip cs2 ce1a gplab3 gpla0 cs1 gplb4 cs4 gplab2 we0 bsa1 bsa2 b c d e d28 clkout d22 d6 d24 d19 d20 d15 d16 d2 d27 d9 d12 d1 d23 d17 pe22 d4 d8 pe25 tsiz0 a31 a22 a18 a25 a24 a20 a29 g h j f a27 a17 a15 a16 a11 a13 a7 a9 a5 a4 a0 pb29 k l vddh m n pe26 pd8 pa1 n/c pb30 pe27 pe20 pe23 mii-tx-en pe17 pe21 pc7 pb19 pb24 tdi tms pc12 pa14 n/c pe15 pe29 pe24 pc13 mii-crs pc10 pb23 pb25 trst gnd p r t pe16 234567 8910111213141516 ipa1 d26 d25 d14 d0 pe18 irq7 irq 1 pa3 pb31 pa0 pe14 pe31 pc6 pa6 pc11 tdo pa15 a3 pa4 pe28 pe30 pa11 mii_col pa7 tck pb28 pc15 pe19 bsa0 bsa3 tsiz1 a26 a28 a30 a23 a21 a14 a19 a10 a12 a2 a8 a1 a6 irq4 vsssyn we1 pa10 d13 d21 vsssyn1 cs6 oe pa2 pb26 pb27 texp 17 u irq0 ipa0 mii_mdio we3 vddh vddh vddh vddh vddh vddh vddh vddh vddl vddl vddl vddl vddl vddl vddl vddl gnd gnd gnd gnd
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 73 mechanical data and ordering information table 36 contains a list of the mpc875/mpc870 input a nd output signals and shows multiplexing and pin assignments. table 36. pin assignments ? jedec standard name pin number type a[0:31] r16, n14, m14, p15, p17, p16, n15, n16, m15, n17, l14, m16, l15, m17, k14, l16, l17, k17, g17, k15, j16, j15, g16, j14, h17, h16, g15, k16, h14, j17, h15, f17 bidirectional three-state (3.3 v only) tsiz0, reg f16 bidirectional three-state (3.3 v only) tsiz1 g14 bidirectional three-state (3.3 v only) rd/wr d13 bidirectional three-state (3.3 v only) burst b9 bidirectional three-state (3.3 v only) bdip , gpl_b5 c13 output ts c11 bidirectional active pull-up (3.3 v only) ta c12 bidirectional active pull-up (3.3 v only) tea b12 open-drain bi b13 bidirectional active pull-up (3.3 v only) irq2 , rsv c9 bidirectional three-state (3.3 v only) irq4 , kr , retry , spkrout e9 bidirectional three-state (3.3 v only) d[0:31] l5, n3, l3, l2, r2, k2, h3, g2, r3, m3, n2, m2, m4, n4, k5, k3, k4, p3, j2, j3, j4, j5, h2, p2, h4, h5, g5, l4, g3, f2, f3, e2 bidirectional three-state (3.3 v only) cr, irq3 e10 input frz, irq6 b10 bidirectional three-state (3.3 v only) br b11 bidirectional (3.3 v only) bg d10 bidirectional (3.3 v only) bb c10 bidirectional active pull-up (3.3 v only) irq0 m6 input (3.3 v only) irq1 p5 input (3.3 v only) irq7 n5 input (3.3 v only) cs [0:5] b14, e11, c14, b15, e13, b16 output
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 74 freescale semiconductor mechanical data and ordering information cs6 , ce1_b f12 output cs7 , ce2_b d15 output we0 , bs_b0, iord e15 output we1 , bs_b1, iowr d17 output we2 , bs_b2, pcoe d16 output we3 , bs_b3, pcwe g13 output bs_a [0:3] f14, e16, e17, f15 output gpl_a0 , gpl_b0 c17 output oe , gpl_a1 , gpl_b1 f13 output gpl_a [2:3], gpl_b [2:3], cs [2?3] e14, c16 output upwaita, gpl_a4 d11 bidirectional (3.3 v only) upwaitb, gpl_b4 e12 bidirectional gpl_a5 d12 output poreset d5 input (3.3 v only) rstconf c3 input (3.3 v only) hreset e7 open-drain sreset c4 open-drain xtal d6 analog output extal d7 analog input (3.3 v only) clkout g4 output extclk b4 input (3.3 v only) texp b3 output ale_a b7 output ce1_a c15 output ce2_a d14 output wait_a d4 input (3.3 v only) ip_a0 g6 input (3.3 v only) ip_a1 f5 input (3.3 v only) ip_a2, iois16_a d3 input (3.3 v only) ip_a3 e4 input (3.3 v only) ip_a4 d2 input (3.3 v only) ip_a5 e3 input (3.3 v only) table 36. pin assignments ? jedec standard (continued) name pin number type
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 75 mechanical data and ordering information ip_a6 f4 input (3.3 v only) ip_a7 c2 input (3.3 v only) ale_b, dsck c8 bidirectional three-state (3.3 v only) ip_b[0:1], iwp[0:1], vfls[0:1] b8, d9 bidirectional (3.3 v only) op0 b6 bidirectional (3.3 v only) op1 c6 output op2, modck1, sts b5 bidirectional (3.3 v only) op3, modck2, dsdo b2 bidirectional (3.3 v only) baddr[28:29] e8, c5 output baddr30, reg d8 output as c7 input (3.3 v only) pa15, usbrxd p14 bidirectional pa14, usboe u16 bidirectional (optional: open-drain) pa11, rxd4, mii1-txd0, rmii1-txd0 r9 bidirectional (optional: open-drain) (5-v tolerant) pa10, mii1-txerr, tin4, clk7 r12 bidirectional (optional: open-drain) (5-v tolerant) pa7, clk1, brgo1, tin1 r11 bidirectional pa6, clk2, tout1 p11 bidirectional pa 4 , c t s 4 , mii1-txd1, rmii-txd1 p7 bidirectional pa3, mii1-rxer, rmii1-rxer, brgo3 r5 bidirectional (5-v tolerant) pa2, mii1-rxdv, rmii1-crs_dv, txd4 n6 bidirectional (5-v tolerant) pa1, mii1-rxd0, rmii1-rxd0, brgo4 t4 bidirectional (5-v tolerant) pa0, mii1-rxd1, rmii1-rxd1, tout4 p6 bidirectional (5-v tolerant) pb31, spisel , mii1-txclk, rmii1-refclk t5 bidirectional (optional: open-drain) (5-v tolerant) table 36. pin assignments ? jedec standard (continued) name pin number type
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 76 freescale semiconductor mechanical data and ordering information pb30, spiclk t17 bidirectional (optional: open-drain) (5-v tolerant) pb29, spimosi r17 bidirectional (optional: open-drain) (5-v tolerant) pb28, spimiso, brgo4 r14 bidirectional (optional: open-drain) (5-v tolerant) pb27, i2csda, brgo1 n13 bidirectional (optional: open-drain) pb26, i2cscl, brgo2 n12 bidirectional (optional: open-drain) pb25, smtxd1 u13 bidirectional (optional: open-drain) (5-v tolerant) pb24, smrxd1 t12 bidirectional (optional: open-drain) (5-v tolerant) pb23, sdack1 , smsyn1 u12 bidirectional (optional: open-drain) pb19, mii1-rxd3, rts4 t11 bidirectional (optional: open-drain) pc15, dreq0 , l1st1 r15 bidirectional (5-v tolerant) pc13, mii1-txd3, sdack1 u9 bidirectional (5-v tolerant) pc12, mii1-txd2, tout1 t15 bidirectional (5-v tolerant) pc11, usbrxp p12 bidirectional pc10, usbrxn, tgate1 u11 bidirectional pc7, cts4 , l1tsyncb, usbtxp t10 bidirectional (5-v tolerant) pc6, cd4 , l1rsyncb, usbtxn p10 bidirectional (5-v tolerant) pd8, rxd4, mii-mdc, rmii-mdc t3 bidirectional (5-v tolerant) pe31, clk8, l1tclkb, mii1-rxclk p9 bidirectional (optional: open-drain) pe30, l1rxdb, mii1-rxd2 r8 bidirectional (optional: open-drain) table 36. pin assignments ? jedec standard (continued) name pin number type
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 77 mechanical data and ordering information pe29, mii2-crs u7 bidirectional (optional: open-drain) pe28, tout3 , mii2-col r7 bidirectional (optional: open-drain) pe27, l1rqb, mii2-rxerr, rmii2-rxerr t6 bidirectional (optional: open-drain) pe26, l1clkob, mii2-rxdv, rmii2-crs_dv t2 bidirectional (optional: open-drain) pe25, rxd4, mii2-rxd3, l1st2 r4 bidirectional (optional: open-drain) pe24, smrxd1, brgo1, mii2-rxd2 u8 bidirectional (optional: open-drain) pe23, txd4, mii2-rxclk, l1st1 u4 bidirectional (optional: open-drain) pe22, tout2, mii2-rxd1, rmii2-rxd1, sdack1 p4 bidirectional (optional: open-drain) pe21, tout1 , mii2-rxd0, rmii2-rxd0 t9 bidirectional (optional: open-drain) pe20, mii2-txer u3 bidirectional (optional: open-drain) pe19, l1txdb, mii2-txen, rmii2-txen r6 bidirectional (optional: open-drain) pe18, smtxd1, mii2-txd3 m5 bidirectional (optional: open-drain) pe17, tin3, clk5, brgo3, smsyn1 , mii2-txd2 t8 bidirectional (optional: open-drain) pe16, l1rclkb, clk6, mii2-txclk, rmii2-refclk u6 bidirectional (optional: open-drain) pe15, tgate1 , mii2-txd1, rmii2-txd1 t7 bidirectional pe14, mii2-txd0, rmii2-txd0 p8 bidirectional tms t14 input (5-v tolerant) tdi, dsdi t13 input (5-v tolerant) tck, dsck r13 input (5-v tolerant) trst u14 input (5-v tolerant) table 36. pin assignments ? jedec standard (continued) name pin number type
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 78 freescale semiconductor mechanical data and ordering information tdo, dsdo p13 output (5-v tolerant) mii1_crs u10 input mii_mdio m13 bidirectional (5-v tolerant) mii1_tx_en, rmii1_tx_en u5 output (5-v tolerant) mii1_col r10 input v sssyn e5 pll analog gnd v sssyn1 f6 pll analog gnd v ddsyn e6 pll analog v dd gnd h8, h9, h10, h11, j8, j9, j10, j11, k8, k9, k10, k11, l8, l9, l10, l11, u15 power v ddl f7, f8, f9, f10, f11, h6, h13, j6, j13, k6, k13, l6, l13, n7, n8, n9, n10, n11 power v ddh g7, g8, g9, g10, g11, g12, h7, h12, j7, j12, k7, k12, l7, l12, m7, m8, m9, m10, m11, m12 power n/c b17, t16, u2, u17 no connect table 36. pin assignments ? jedec standard (continued) name pin number type
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 79 mechanical data and ordering information 16.2 mechanical dimensions of the pbga package figure 70 shows the mechanical dimensions of the pbga package. . figure 70. mechanical dimensions and bottom surface nomenclature of the pbga package note : solder sphere composition is 95.5%sn 45%ag 0.5%cu for mpc875/mpc870vrxxx. solder sphere composition is 62%sn 36%pb 2%ag for mpc875/mpc870ztxxx. 1. all dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m?1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. notes:
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 80 freescale semiconductor document revision history 17 document revision history table 37 lists significant changes between revisions of this hardware specification. table 37. document revision history revision number date changes 0 2/2003 initial release. 0.1 3/2003 took out the time-slot assigner and changed the scc for scc3 to scc4. 0.2 5/2003 changed the package drawing, removed all references to data parity. changed the spi master timing specs. 162 and 164. added the rmii and usb timing. added the 80-mhz timing. 0.3 5/2003 made sure the pin types were correct. changed the features list to agree with the mpc885. 0.4 5/2003 corrected the signals that had overlines on them. made corrections on two pins that were typos. 0.5 5/2003 changed the pin descriptions for pd8 and pd9. 0.6 5/2003 changed a few typos. put back the i 2 c. put in the new reset configuration, corrected the usb timing. 0.7 6/2003 changed the pin descriptions per the june 22 spec, removed utopia from the pin descriptions, changed padir, pbdir, pcdir and pddir to be 0 in the mandatory reset config. 0.8 8/2003 added the reference to usb 2.0 to the features list and removed 1.1 from usb on the block diagrams. 0.9 8/2003 changed the usb description to full-/low-speed compatible. 1.0 9/2003 added the dsp information in the features list. put a new sentence under mechanical dimensions. fixed table formatting. nontechnical edits. released to the external web. 1.1 10/2003 added tdmb to the mpc875 features list, the mpc875 block diagram, added 13.5 serial interface ac electrical specifications, and removed tdma from the pin descriptions. 2.0 12/2003 changed dbgc in the mandatory reset configuration to x1. changed the maximum operating frequency to 133 mhz. put the timing in the 80 mhz column. put in the orderable part numbers. rounded the timings to hundredths in the 80 mhz column. put the pin numbers in footnotes by the maximum currents in table 6. changed 22 and 41 in the timing. put tbd in the thermal table.
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 81 document revision history 3.0 1/07/2004 7/19/2004 ? added sentence to spec b1a about extclk and clkout being in alignment for integer values. ? added a footnote to spec 41 specifying that edm = 1. ? added the thermal numbers to table 4. ? added rmii1_en under m1ii_en in table 36, pin assignments. ? added a table footnote to table 6, dc electrical specifications, about meeting the v il max of the i 2 c standard. ? put the new part numbers in the ordering information section. 4 08/2007 ? updated template. ? on page 1, updated first paragraph and added a second paragraph. ? after table 2, inserted a new figure showing the undershoot/overshoot voltage ( figure 3 ) and renumbered the rest of the figures. ?in ta b l e 1 0 , for reset timings b29f and b29g added footnote indicating that the formula only applies to bus operation up to 50 mhz. ?in figure 5 , changed all reference voltage measurement points from 0.2 and 0.8 v to 50% level. ?in ta b l e 1 8 , changed num 46 description to read, ?ta assertion to rising edge ...? ?in figure 43 , changed ta to reflect the rising edge of the clock. table 37. document revision history (continued) revision number date changes
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 82 freescale semiconductor document revision history this page intentionally left blank
mpc875/mpc870 powerquicc? hardware specifications, rev. 4 freescale semiconductor 83 document revision history this page intentionally left blank
document number: mpc875ec rev. 4 08/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ieee 802.3, 802.11i, and 1149.1 are trademarks or registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2003?2007. all rights reserved.

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